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The Nanoscope: Big News in Small Science
IEN News

Mixed-signal Processing Powers Bio-mimetic CMOS Chip to Enable Neural Learning in Autonomous Micro-Robots

In a recent publication and live demonstration at the International Solid State Circuits Conference (ISSCC), researchers from the Georgia Institute of Technology have used analog processing to squeeze a 3.12Top/W (average) artificial intelligence processor onto a CMOS (55nm) chip, consuming only 690μW (1.2V), and aimed at self-teaching micro-robots that need to learn their immediate environments. The processor implements ‘reinforcement learning’ – a behaviorist psychology-inspired learning algorithm that mimics the way dopamine encourages reward-motivated behavior in human social interactions. The paper is authored by Electrical and Computer Engineering graduate researchers - Anvesha Amravati, Saad Bin Nasir, Sivaram Thangadurai, Insik Yoon and their doctoral advisor Professor Arijit Raychowdhury. The writing team was assisted in a live demonstration by Justin Ting, an undergraduate also in the Department of Electrical and Computer Engineering.




The paper, presented on February 12, 2018 at the International Solid-State Circuits Conference (ISSCC), states that the test chip inherits properties of stochastic neural networks and recent advances in Q-learning. Mixed-signal processing was adopted. rather than an all-digital approach, to save area and power. Executing the neural learning based algorithms requires the equivalent of 4 to 8 bits (1:16 to 1:256) accuracy, according to the research team, which rules out analogue voltage computation because of the limiting effect of low supply voltage on dynamic range. Instead, analog pulse-widths have been used, thereby enabling large dynamic ranges. As a trade-off, the architectures are slower, but not to the point at which they become unacceptable for the applications in hand”.

As an example of the mixed signal processing within a time-domain neuron, a time-domain multiply-and-accumulate (MAC) is implemented in a 21-bit counter which multiplies the 6-bit input from a pre-synaptic neuron by the 6-bit weight of the synapse. The counter’s input is a pulse whose width is proportional to the input value, and the counter is clocked by a frequency proportional to the learned weighting, with the result that the count is proportional to one multiplied by the other. Using an up/down counter allows negative values of input to be accommodated.

This process looks typically digital up to this point, however the weighing-to-frequency oscillator appears to be based on binary-weighted current sources – implemented as memory-in-logic to reduce data movement.

“The energy to perform a MAC is proportional to the magnitude of the operands and hence the importance of the computation in the neural network, a feature inherent in the brain but missing in digital logic,” said the team. The worst-case useable power observed is 1.25pJ/MAC at 0.8V.

A micro-robot used to demonstrate the processing algorithm was designed to measure distance using ultra-sonic sensors and to use the 4.5mm2, 55nm test--chip to control its direction of motion. The measured peak energy efficiency of the developed demonstrator is at 0.8V, with 690pJ/inference and 1.5nJ/training cycle.

According to Professor Raychowdhury, “This paper presents the first reported integrated circuit which implements reinforcement learning at less than a milli-Watt. This can enable a wide variety of applications in autonomous and bio-mimetic systems.”


ISSCC paper 7.4 - A 55nm Time-domain mixed-signal neuromorphic accelerator with stochastic synapses and embedded reinforcement learning for autonomous micro-robot.
News Release at Electronics Weekly

 

IEN Affiliates Receive NSF CAREER Awards

Congratulations to Professors Fathi Sarioglu and Omer T. Inan on receiving an NSF CAREER Award for their emerging research.

Sarioglu, a Assistant Professor in the School of Electrical and Computer Engineering, will be focused on technologies that can assist in the rapid  characterization of blood samples and extraction reliable diagnostic information from samples.

Inan is an Assistant Professor in the School of Electrical and Computer Engineering. His research project is entitled “Wearable Joint Sounds Sensing for Children with Juvenile Idiopathic Arthritis.” This project will focus on researching wearable joint health sensing systems for persons with JIA that will allow for continuous assessment both in and out of the clinic.

Read more on Sarioglu's Award here .
Read more about Inan's Award here.

Sarvey Selected for IEEE Best Paper Award

Tom Sarvey has been named the recipient of the 2017 Best Paper Award for the IEEE Transactions on Components, Packaging, and Manufacturing Technology in the Components: Characterization and Modeling category. He is a Ph.D. student in the Georgia Tech School of Electrical and Computer Engineering (ECE) and is a member of the Integrated 3D System (I3DS) Group.

Sarvey will be recognized for the paper entitled "Monolithic Integration of a Micropin-Fin Heat Sink in a 28-nm FPGA” at the 2018 IEEE Electronic Components and Technology Conference. The conference will be held May 29-June 1 in San Diego, California.

Read More Here.

Cleanroom Corner

Presenting the Elionix ELS-G100 E-Beam
Lithography System

 

The IEN Inorganic Cleanroom houses the brand new Elionix ELS-G100 E-Beam Lithography System. The ELS-G100 is a high speed, high precision thermal field emission (TFE) electron beam lithography system that’s capable of generating patterns with a 7nm line width. These uniform lines can be drawn from edge-to-edge of a 500μm field without stitching. The ELS G-100 is designed to have high precision beams, long-term stability, and high throughput to meet your needs for all nanometric applications.

The new tool is compatible with a wide variety of commercially available resists, and possess an 8-inch stage for project variability.

For more information contact Devin Brown at devin.brown@ien.gatech.edu
Education News
An introduction to the NSF-funded National Nanotechnology Coordinated Infrastructure, a network of user research facilities headquartered at the Institute for Electronics and Nanotechnology At Georgia Tech.
Professional Development

NanoFANS 2018 - Event Focus: Biophotonics in Medical Diagnostics

May 9, 2018 | Marcus Nanotechnology Building

Nanotechnology Events
CANCELLED: Nano@Tech: Suren Chavan, Vicapsys
Tuesday April 10, 2018 @ 12PM
Marcus Nanotech - 1117


Nano@Tech: Dragomir Davidovic, Physics, Georgia Tech
Tuesday April 24, 2018 @ 12PM
Marcus Nanotech - 1117
Nanovation Podcast With Professor Michael Filler -
Featuring Elizabeth Nance - Why I’m fascinated by diffusion



Elizabeth Nance from the University of Washington talks about the use of nanoparticles to treat neurological diseases. We discuss what makes nanoparticles such interesting vehicles for delivering drugs to the brain, how her lab interrogates this process, and why laboratory success so often fails to translate into people. Elizabeth also shares her perspective on how to train future scientists and engineers to operate in a complex, interdisciplinary world. When a conversation begins with a story of a stolen brain, you know it's going to be good!

Listen to the podcast, and check out the archives, here!
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