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The Nanoscope: Big News in Small Science
IEN News
Georgia Tech’s Center for Co-Design of Chip, Package System (C3PS) Partners with Notre Dame in $26 Million Multi-University Research Center Developing Next-Generation Computing Technologies

In today’s era of big data, cloud computing, and Internet of Things devices, information is produced and shared on a scale that challenges the current processing speeds and energy load demands placed on electronics devices. These challenges are only set to expand, as the ability to create and store data increases in magnitude over the next decade.
With these computing challenges in mind, the Semiconductor Research Corporation's (SRC) Joint University Microelectronics Program (JUMP), which represents a consortium of industrial participants and the Defense Advanced Research Projects Agency (DARPA), has established a new $26 million center called the Applications and Systems-driven Center for Energy-Efficient integrated Nano Technologies (ASCENT).
Georgia Tech’s Center for Co-design of, Chip, Package System (C3PS) led by Profs. M. Swaminathan and A. Raychowdhury, director and deputy director, respectively, both from the School of Electrical and Computer Engineering, and with support from the Institute of Electronics and Nanotechnology, headed-up Georgia Tech’s winning proposal that resulted in a 5 year, $3.5M award that will fund up to 10 GRA positions.
The multidisciplinary, multi-university center will focus on conducting research that aims to increase the performance, efficiency and capabilities of future computing systems for both commercial and defense applications. By going beyond current industry approaches, such as two dimensional scaling and the addition of performance boosters to complementary metal oxide semiconductors, or CMOS technology, the GT team seeks to provide enhanced performance and energy consumption at lower costs.
Profs. Raychowdhury(PI) and Swaminathan(co-PI) will work in the area of heterogeneous integration, with a focus on the design of high speed die-to-die networks, the incorporation of power, logic, memory and RF components on a common substrate that enables 2.5D and 3D integration.
“Our involvement in the ASCENT center provides us with a unique opportunities to partner with the academic and industrial leaders to explore foundational technologies in computing. We will leverage our expertise on high-speed circuit design, device-circuit interactions and advanced packaging to address logic and memory challenges for next-generation computing and communication systems,” said Prof Raychowdhury, the ON Semiconductor Jr Associate Professor of VLSI Systems.
“Georgia Tech has always had a long history of working with SRC and we are therefore excited and honored to continue that effort through JUMP,” said Prof. M. Swaminathan, John Pippin Chair in Microsystems Packaging & Electromagnetics and C3PS director. “Through JUMP we plan on expanding our current center capabilities on power delivery, machine learning, multi-physics simulation and system design to include new circuit architectures, power converters, magnetic materials, high frequency components, vertically integrated tools and other platform technologies on a common interconnect fabric.”
This is the one of the largest JUMP such centers funded by SRC and will work synergistically over the next five years to provide breakthrough technologies.  Other universities involved in the 13-member team include; Notre Dame (lead), Arizona State University, Cornell University, Purdue University, Stanford University, University of Minnesota, University of California-Berkeley, University of California-Los Angeles, University of California-San Diego, University of California-Santa Barbara, University of Colorado, and the University of Texas-Dallas.

Congratulations to Saibal Mukhopadhyay - Elevated to IEEE Fellow

ECE Professor, and C3PS Faculty Member, Professor Saibal Mukhopadhyay has been elevated to the level if IEEE Fellow “for contributions to energy-efficient and robust computing systems design”.Professor Saibal Mukhopadhyay received the bachelor of engineering degree in electronics and telecommunication engineering from Jadavpur University, Calcutta, India in 2000 and the Ph.D. degree in electrical and computer engineering from Purdue University, West Lafayette, IN, in August 2006. Dr. Mukhopadhyay worked at IBM T. J. Watson Research Center, Yorktown Heights, N.Y. as research staff member from August 2006 to September 2007 and as an intern in summers of 2003, 2004, and 2005. At IBM, his research primarily focused on technology-circuit co-design methodologies for low-power and variation tolerant static random access memory (SRAM) in sub-65nm silicon technologies. He joined the faculty of the Georgia Institute of Technology in September 2007.

Researchers Boost Efficiency and Stability of
Optical Rectennas

The research team that announced the first optical rectenna in 2015 is now reporting a two-fold efficiency improvement in the devices — and a switch to air-stable diode materials. The improvements could allow the rectennas – which convert electromagnetic fields at optical frequencies directly to electrical current – to operate low-power devices such as temperature sensors.

"This work takes a significant leap forward in both fundamental understanding and practical efficiency for the optical rectenna device,” said Baratunde Cola, an associate professor in the George W. Woodruff School of Mechanical Engineering at the Georgia Institute of Technology. “It opens up this technology to many more researchers who can join forces with us to advance the optical rectenna technology to help power a range of applications, including space flight.”

Read More Here.

Cleanroom Corner

CtrLayer SDS – Aluminum Nitride Sputterer

The CtrLayer SDS - AlN Sputtering System is an in-house fabricated dedicated high quality aluminum nitride deposition tool. It uses a calibration algorithm to generate recipes that maintain a high uniformity despite a small target and short target to substrate distance. It is currently outfitted with three sputtering guns dedicated for reactive aluminum nitride, molybdenum and sputtered aluminum nitride.

The CtrLayer SDS primarily uses reactive sputtering, a technique widely used in industrial and R&D sectors, to apply precise thin films while maintaining a high coating deposition rate. The piezoelectric thin films created in the reactive sputtering process can be used in a variety of applications including solar cells, optical components, flat panel displays and microelectronic mechanical systems.

Click to visit the SDS – Aluminum Nitride Sputterer on SUMS

For Training or Process Questions, Contact Charlie Suh:
Education News
The Institute for Electronics and Nanotechnology - 2018 Summer Undergraduate Research Program In Nanotechnology

A program of SENIC at the Institute for Electronics and Nanotechnology, Georgia Institute of Technology. Explore exciting interdisciplinary opportunities in nanoscale science and engineering at Georgia Tech’s IEN facilities.


Applications accepted now through Feb. 16, 2018 (Click here)!

Note: Georgia Tech students are NOT eligible for the SUIN Program, but they can apply for other internship programs within the NNCI.

Funding News
Mentored Career Development & Training Opportunities from the Georgia Clinical & Translational Science  Alliance

Competitive Opportunities & Deadlines:
  • KL2 Mentored Clinical & Translational Research Junior Faculty Scholar grant Due March 1
  • TL1 (T32-like) grants:
    PhD student training – Due February 15
    Post-doctoral training – Due March 15  

Find Full Details Regarding Application and Requirements Here

Nanotechnology Events

IEN Short Course: Microfabrication

March 19-21, 2018 | Marcus Nanotechnology Building

The Institute for Electronics and Nanotechnology (IEN) at Georgia Tech will offer a short course on micro-fabrication from March 19 - 21, 2018. This in­tensive 3 day short course combines classroom lectures and laboratory based hands-on fabrication in the IEN cleanroom. The goal of the course is to impart a basic understanding of the science and technology of micro-fabrication processes as used in academia and industry.

This short course will cover essential micro-fabrication techniques including, photolithography, thin film deposition, etching, packaging, and characterization. Attendees will gain valuable experience by fabricating simple devices in one of the most advanced university cleanrooms in North America.

Target Audience

Attendance is open to the general technical community and is not limited to current Georgia Tech students or IEN users. Anyone interested in cleanroom fabrication techniques is strongly encouraged to attend this course. The course is suitable for both new and experienced researchers interested in micro-fabrication techniques and applications.

A course emphasis will be placed on IEN cleanroom resources, however, the concepts and techniques discussed are applicable to a broad array of research in this field.

Rates: *Rates include lunches on all days*

  • Georgia Tech Rate: $200
  • Academic and Government Rate: $400
  • Industry Rate: $800

IEN Short Course: Soft Lithography for Microfluidics

April 26-27, 2018 | Marcus Nanotechnology Building

The Institute for Electronics and Nanotechnology (IEN) at Georgia Tech will offer a short course on “Soft Lithography for Microfluidics” on April 26 & 27, 2018. This course module is designed for individuals interested in hands-on training in the fabrication of microfluidic devices using the soft lithography technique.

This 2 day intensive short course will be structured to assume no prior knowledge of the technologies by the participants. The course agenda is evenly divided between laboratory hands-on sessions, including SU-8 master mold creation using photolithography and PDMS device fabrication in the IEN cleanroom, and supporting lectures. The goal for this course is to impart a basic understanding of soft lithography for microfluidic applications as practiced in academia and industry.

Target Audience
This short course is open to off-campus researchers from academia, industry and government laboratories/organizations and is not limited to current Georgia Tech students or IEN users. Anyone who is interested in starting research in the area of microfluidics or PDMS device fabrication is invited and strongly encouraged to participate.

Rates: *Rates include lunches on all days*
Georgia Tech Rate: $150
Academic and Government Rate: $300
Industry Rate: $600

Nano@Tech: Nonlinear Interactions in Nano/Microelectromechanical Systems (N/MEMS)
Tuesday February 13, 2018 @ 12PM
Marcus Nanotech - 1117

Full abstract and bio here.

Nano@Tech: MEMS- Based Hemodynamic Monitoring for Advanced Heart Failure Management
Tuesday February 27, 2018 @ 12PM
Marcus Nanotech - 1117

Full abstract and bio here.
Nanovation Podcast With Professor Michael Filler -
Featuring Andrew Cannon of 1900 Engineering

Andrew Cannon started 1900 Engineering to commercialize a microcontact printing-based technology to map strain in high performance materials. His technology helps engineers understand when and how parts fatigue, knowledge that is critically important for industries ranging from aerospace to automotive. We talk about how 1900 Engineering's technology works and how the stamps are fabricated, but also discuss a number of the long-standing challenges to precision patterning at the micrometer and nanometer length scale.  

Listen to the podcast, and check out the archives, here!
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Georgia Institute for Technology

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